1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same.
2. Description of the Related Art
In recent years, semiconductor devices have been becoming smaller and more highly integrated. Along with this trend, more and more wrong operations and unstable characteristics are seen in a semiconductor device due to interference between regions having different functions.
In view of this, there has been an increasing demand for semiconductors in which no interference is caused between regions having different functions.
FIGS. 11A and 11B are a sectional view and a perspective view of a conventional semiconductor device. A CSP (Chip Size Package) semiconductor device is shown in the figures.
In a conventional semiconductor device 81 shown in FIG. 11A, a semiconductor chip 82 is sealed in a resin package 83. Signal terminals on the surface of the semiconductor chip 82 are electrically connected to mounting protrusions 85 protruding from the bottom surface of the resin package 83 by wires 84.
The surfaces of the mounting protrusions are covered with metal films 86, and the bottom surface of the semiconductor chip 82 is coated with an insulating adhesive 89.
As shown in FIG. 11B, the semiconductor chip 82 is situated in the center of the semiconductor device 81, and the metal films 86 (or the mounting protrusions 85) are situated in the surrounding area of the semiconductor chip 82. The metal films 86 are connected to the signal terminals of the semiconductor chip 82 by the wires 84.
The signal terminals of the semiconductor chip 82 include terminals which input and output various signals, and a grounding terminal which serves as a reference potential.
Since semiconductor devices have been becoming smaller and more highly integrated, regions having various functions exist in a small area. FIG. 12 is an enlarged sectional view of a part of the conventional semiconductor device, illustrating the problems in the prior art.
The semiconductor device 81 shown in FIG. 12 has a PLL (Phase Locked Loop) circuit, for instance. The semiconductor chip 82 contains a plurality of functional regions including a first functional region 90 and a second functional region 91. The functional regions are formed with a semiconductor substrate 87 as a base, and are divided by isolators 92.
A wiring pattern 93 is formed on the surfaces of the first functional region 90 and the second functional region 91, and a part of the wiring pattern 93 is connected to a grounding terminal 94 which is a reference potential. The grounding terminal 94 also serves to release small noise existing inside the semiconductor substrate 87, and is formed on one of the isolators 92.
The bottom surface of the semiconductor chip 82, i.e., the bottom surface of the semiconductor substrate 87, is coated with the insulating adhesive 89.
Since the semiconductor device 81 is extremely small and highly integrated, the first functional region 90 and the second functional region 91 are disposed in an extremely small area, though they have different functions.
In the PLL circuit, frequency conversion is performed by a divider to generate a plurality of frequencies. For instance, the first functional region 90 operates on a frequency f1, while the second functional region 91 operates on a different frequency f2.
With such a structure, the frequency leaking from each region turns into noise that enters the neighboring functional region, as indicated by arrows in FIG. 12. The noise often results in unstable characteristics or wrong operations.
The grounding terminal 94 disposed on the isolator 92 cannot release enough noise, because the first functional region 90 and the second functional region 91 are too close to each other. It is possible to release all noise by forming a plurality of grounding terminals at short intervals, but such a measure is not suitable for the highly-integrated small-size semiconductor device.